1/10 february 2003 n high speed: t pd = 5.0 ns (typ.) at v cc =5v n low power dissipation: i cc =8 m a(max.) at t a =25c n high noise immunity: v nih =v nil =28%v cc (min.) n 50 w trasmission line driving capability n symmetrical output impedance: |i oh |=i ol = 24ma (min) n operating voltage range: v cc (opr) = 2v to 6v n improved latch-up immunity description the 74ac16373 cmos 16 bit d-type latch with 3 state outputs non inverting fabricated with sub-micron silicon gate and double-layer metal wiring c 2 mos technology. these 16 bit d-type latches are byte controlled by two latch enable inputs (nle) and two output enable inputs(noe ). while the nle input is held at a high level, the nq outputs will follow the data (d) inputs. when the nle is taken low, the nq outputs will be latched at the logic level of d data inputs. when the (noe ) input is low, the nq outputs will be in a normal logic state (high or low logic level); when noe is at high level ,the outputs will be in a high impedance state. all inputs and outputs are equipped with protection circuits against static discharge, giving them 2kv esd immunity and transient excess voltage. 74ac16373 16-bit d-type flip-flop with 3-state outputs (non inverted) order codes package tube t & r tssop 74AC16373TTR tssop pin connection
74ac16373 2/10 input and output equivalent circuit pin description truth table x : dont care z : high impedance * : q outputs are latched at the time when the le input is taken low logic level. iec logic symbols pin no symbol name and function 1 1oe 3 state output enable input (active low) 2, 3, 5, 6, 8, 9, 11, 12 1q0 to 1q7 3-state outputs 13, 14, 16, 17, 19, 20, 22, 23 2q0 to 2q7 3-state outputs 24 2oe 3 state output enable input (active low) 25 2le latch enable input 36, 35, 33, 32, 30, 29, 27, 26 2d0 to 2d7 data inputs 47, 46, 44, 43, 41, 40, 38, 37 1d0 to 1d7 data inputs 48 1le latch enable input 4, 10, 15, 21, 28, 34, 39, 45 gnd ground (0v) 7, 18, 31, 42 v cc positive supply voltage inputs output oe le d q hxx z l l x no change * lhl l lhh h
74ac16373 3/10 logic diagram this logic diagram has not to be used to estimate propagation delays absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. recommended operating conditions 1) v in from 30% to 70% of v cc symbol parameter value unit v cc supply voltage -0.5 to +7 v v i dc input voltage -0.5 to v cc + 0.5 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 20 ma i o dc output current 50 ma i cc or i gnd dc v cc or ground current 400 ma t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage 2to6 v v i input voltage 0 to v cc v v o output voltage 0 to v cc v t op operating temperature -55 to 125 c dt/dv input rise and fall time v cc = 3.0, 4.5 or 5.5v (note 1) 8 ns/v
74ac16373 4/10 dc specifications 1) maximum test duration 2ms, one output loaded at time 2) incident wave switching is guaranteed on transmission lines with impedances as low as 50 w symbol parameter test condition value unit v cc (v) t a =25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v ih high level input voltage 3.0 v o = 0.1 v or v cc -0.1v 2.1 1.5 2.1 2.1 v 4.5 3.15 2.25 3.15 3.15 5.5 3.85 2.75 3.85 3.85 v il low level input voltage 3.0 v o = 0.1 v or v cc -0.1v 1.5 0.9 0.9 0.9 v 4.5 2.25 1.35 1.35 1.35 5.5 2.75 1.65 1.65 1.65 v oh high level output voltage 3.0 i o =-50 m a 2.9 2.99 2.9 2.9 v 4.5 i o =-50 m a 4.4 4.49 4.4 4.4 5.5 i o =-50 m a 5.4 5.49 5.4 5.4 3.0 i o =-12 ma 2.56 2.46 2.46 4.5 i o =-24 ma 3.86 3.76 3.76 5.5 i o =-24 ma 4.86 4.76 4.76 v ol low level output voltage 3.0 i o =50 m a 0.002 0.1 0.1 0.1 v 4.5 i o =50 m a 0.001 0.1 0.1 0.1 5.5 i o =50 m a 0.001 0.1 0.1 0.1 3.0 i o =12 ma 0.36 0.44 0.44 4.5 i o =24 ma 0.36 0.44 0.44 5.5 i o =24 ma 0.36 0.44 0.44 i i input leakage current 5.5 v i =v cc or gnd 0.1 1 1 m a i oz high impedance output leakage current 5.5 v i =v ih or v il v o =v cc or gnd 0.5 5 5 m a i cc quiescent supply current 5.5 v i =v cc or gnd 88080 m a i old dynamic output current (note 1, 2) 5.5 v old = 1.65 v max 75 75 ma i ohd v ohd = 3.85 v min -75 -75 ma
74ac16373 5/10 ac electrical characteristics (c l =50pf,r l = 500 w , input t r =t f =3ns) (*) voltage range is 3.3v 0.3v (**) voltage range is 5.0v 0.5v capacitive characteristics 1) c pd is defined as the value of the ics internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) =c pd xv cc xf in +i cc /16 (per circuit) symbol parameter test condition value unit v cc (v) t a =25c -40 to 85 c -55 to 125c min. typ. max. min. max. min. max. t plh t phl propagation delay time le to q 3.3 (*) 8.0 10.0 15.6 15.6 ns 5.0 (**) 6.0 8.0 11.9 11.9 t plh t phl propagation delay time dtoq 3.3 (*) 8.3 11.0 15.1 15.1 ns 5.0 (**) 6.0 9.1 10.1 10.1 t pzl t pzh output enable time 3.3 (*) 11.8 19.8 22.3 22.3 ns 5.0 (**) 7.4 11.3 12.8 12.8 t plz t phz output disable time 3.3 (*) 7.1 9.5 10.2 10.2 ns 5.0 (**) 5.9 8.0 8.8 8.8 t w le pulse width high 3.3 (*) 4.0 4.0 4.0 ns 5.0 (**) 5.0 5.0 5.0 t s setup time d to le, high or low 3.3 (*) 1.5 1.5 1.5 ns 5.0 (**) 1.5 1.5 1.5 t h hold time d to le, high or low 3.3 (*) 333 ns 5.0 (**) 2.5 2.5 2.5 symbol parameter test condition value unit v cc (v) t a =25c -40 to 85 c -55 to 125c min. typ. max. min. max. min. max. c in input capacitance 5.0 3.5 pf c out output capaci- tance 5.0 15 pf c pd power dissipation capacitance (note 1) 5.0 f in =10mhz 25 pf
74ac16373 6/10 test circuit c l = 50pf or equivalent (includes jig and probe capacitance) r l =r 1 =500 w or equivalent r t =z out of pulse generator (typically 50 w ) waveform 1 : le to qn propagation delays, le minimum pulse width, dn to le setup and hold times (f=1mhz; 50% duty cycle) test switch t plh, t phl open t pzl, t plz 2v cc t pzh, t phz gnd
74ac16373 7/10 waveform 2: output enable and disable time (f=1mhz; 50% duty cycle) waveform 3 : propagation delay time (f=1mhz; 50% duty cycle)
74ac16373 8/10 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.006 a2 0.9 0.035 b 0.17 0.27 0.0067 0.011 c 0.09 0.20 0.0035 0.0079 d 12.4 12.6 0.488 0.496 e 8.1 bsc 0.318 bsc e1 6.0 6.2 0.236 0.244 e 0.5 bsc 0.0197 bsc k0? 8?0? 8? l 0.50 0.75 0.020 0.030 tssop48 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 7065588c
74ac16373 9/10 dim. mm. inch min. typ max. min. typ. max. a 330 12.992 c 12.8 13.2 0.504 0.519 d 20.2 0.795 n 60 2.362 t 30.4 1.197 ao 8.7 8.9 0.343 0.350 bo 13.1 13.3 0.516 0.524 ko 1.5 1.7 0.059 0.067 po 3.9 4.1 0.153 0.161 p 11.9 12.1 0.468 0.476 tape & reel tssop48 mechanical data
74ac16373 10/10 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco singapore - spain - sweden - switzerland - united kingdom - united states. ? http://www.st.com
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